FB-DIMMs provide larger memory capacities for servers and workstations, higher operational reliability and easier serviceability. Current FB-DIMMs support DDR2-SDRAM memory packages only. Next to a plurality of memory packages, each FB-DIMM includes a special AMB (AMB=Advanced Memory Buffer). The AMB sets up, for example, a serial link to a memory controller not located on the FB-DIMM via an input/output interface including 24 differential line pairs. Typically, control information and data reach the AMB from the memory controller via 10 of the 24 signal line pairs, the AMB in turn deriving therefrom corresponding control information and data for the memory packages on the FB-DIMM and passing same thereto. The interfacing from the memory controller to the AMBs is also referred to as southbound or inbound link. Vice-versa, the link from the FB-DIMM in the direction of the memory controller via 14 line pairs is also referred to as northbound or outbound link.
The FB-DIMM technology manages a maximum of eight modules, that is FB-DIMMs, per memory channel. This means that eight FB-DIMMs may be connected in series to a memory channel of a memory controller. Here, the AMBs form an asynchronous latch chain for the ingoing data in the form of a daisy chain.
Up to 36 memory packages are permitted on an FB-DIMM. As a rule, next to the AMB 18 DDR2-SDRAM memory packages are located on an FB-DIMM loaded on both sides. An additional 18 memory packages may be connected on the module my means of the stacked method. As a result, a memory controller may drive up to 36*8=288 memory packages per memory channel.
AMB-ICs are the central component of FB-DIMMs. By means of a special bus architecture, i.e., the daisy chain architecture mentioned above, a plurality of FB-DIMMs is typically connected in series. Here, there is a point-to-point link between the memory controller and a first FB-DIMM and from the first FB-DIMM to a succeeding FB-DIMM or memory module, etc. This structure makes it possible to access the bus independently of a speed of the SDRAM I/O, whereby both a larger memory capacity and higher speeds are made possible.
In the daisy chain, the AMB Chip captures the ingoing data, that is frames of payload and/or write data, addresses and commands from the preceding FB-DIMM or the memory controller and transmits the same to the subsequent FB-DIMM. Frames destined for their own FB-DIMM, on the basis of their address, are reprocessed by the AMB in order to correspondingly drive the memory packages on this DIMM. Therefore, the AMBs provide distribution of the data among the SDRAM packages.
The FB-DIMM standard provides for data multiplexing with a factor 6. This means that DRAM frames are transmitted from the memory controller to the AMB by means of a 6:1 multiplexer. There, a respective logic demulitplexes the datastream received and passes the extracted information to the individual SDRAM memory chips. For this data exchange, the FB-DIMM technology utilizes a deterministic RAS/CAS protocol. The memory controller and the memory are thus guaranteed to be subject to a controlled repetitive process at each point in time due to self-contained data packets. Simultaneously, the FB-DIMM protocol optimizes memory access to the various FB-DIMMs and therefore significantly increases memory performance.
The FB-DIMM protocol knows two types of data frames. Via the 10-bit wide southbound link, command frames reach the FB-DIMMs, and via the 14-bit wide northbound link, the memory controller receives response frames containing payload data read from the DRAMs.
Current FB-DIMMs with a corresponding AMB are configured for DDR2-SDRAM memory packages. DDR2-SDRAM is a refinement of the DDR-SDRAM concept, wherein a four-fold prefetch is used instead of a double prefetch. In the former DDR standard, valid data was obtained both on the rising and on the falling edge of the clock signal. With DDR2, additional valid data is received in-between these states, which results in four data words per clock. With DDR2-SDRAM, an I/O buffer clocks at a double frequency of the memory packages.
Future FB-DIMMs, so-called FB-DIMM2s, are to be populated with DDR3-SDRAM packages. DDR3-SDRAM is a refinement of the DDR2-SDRAM concept, wherein an eight-fold prefetch is used instead of a four-fold prefetch. In addition, DDR3-SDRAM necessitates a supply voltage of only 1.5 volts, compared to a supply voltage of 1.8 volts for a DDR2-SDRAM and is significantly faster than current DDR and DDR2 memory packages on the basis of the eight-fold prefetch. Therefore, altered AMB2s will have to be employed in future FB-DIMM2 modules compared to the AMBs for DDR2, in order to be able to supply, for example, the higher rotation rates for the DDR3 packages.
Typically, there are several clock frequencies and rotation rates in and around an AMB, which are in a fixed relation to one another. The magnitude of an FBD data rate (FBD=Fully Buffered DIMM) fFBD, for example, is 12 times larger than a core clock frequency fcore. Here, the FBD data rate designates the data rate of the southbound and northbound links, that is the data rate on one of the 10 bit-line or line-pair links of the southbound link, whereon the frames are transferred by 120 bits each. The magnitude of a DDR2 data rate fDDR2 is two times larger than the core clock frequency fcore of the AMB. Here, the DDR2 data rate stands for the payload or write/read data rate with which the DDR2 memory packages may be written to and/or read from, wherein currently DDR2 memory packages with four or eight of such I/O terminals operating with fDDR2 are available. fDDR2 amounts to one-sixth of the FBD data rate fFBD. The core clock frequency fcore is equal to a DDR2 command clock frequency fcmd and is two times larger than an external reference clock frequency fref. The command clock frequency stands for the clock frequency with which commands from the AMB may be transmitted to the memory packages. A relation between the various clock frequencies will remain constant.
The following table exemplarily illustrates a relation of the data rates and frequencies described above.
freffcorefDDR2FFBD133 MHz266 MHz533 Mbit/s3.2 Gbit/s167 MHz333 MHz667 Mbit/s4.0 Gbit/s200 MHz400 MHz800 Mbit/s4.8 Gbit/s